The development of increasingly complex integrated circuits with very high input/output (I/O) counts has been coupled with increasing clock rates to compel the development of new manufacturing techniques. In addition, the number of electronic devices that require portability is constantly growing, thereby compelling reductions in system size and weight without adversely affecting reliability. Further adding to this is the advent of the broadband which has greatly increased the requirements for signal transmission in integrated devices and their packaging. Because of these trends, printed circuit board assemblies must rely on increasingly dense interconnection with finer lines, smaller blind or through holes or vias through chip carriers and decreasing thickness of the entire assembly.
One factor in further reducing the size and weight of these components is the ability to electrically couple the chips to the printed circuit board so that the signals from the chip are arrayed to all necessary locations on the board as efficiently as possible.
There are several technologies, such as wire bonding and flip chip mounting, for connecting a chip to a carrier. One type of flip chip mounting, a controlled collapse chip connection (commonly referred to in the industry as C4), is a chip output that is designed so that the chip can be connected through a chip carrier to a printed circuit board. Initially, the C4 technology was limited to ceramic substrates due to the adverse effect that high temperatures required to reflow the tin solder on the chips had on the need to match the thermal expansion of the carrier substrate and that of the silicon chip. However, with the development of low cost dielectrics, such as FR-4 and standard reflow joining time/temperature profiles, this problem is no longer insurmountable. A controlled expansion epoxy encapsulated between the chip and the carrier is used to minimize the cyclic strain on the solder joints induced by thermal expansion mismatch between the chip and the substrate. Without the use of the encapsulant, the thermal cycle fatigue life of the joints would be unacceptable. A typical C4 structure comprises a silicon semiconductor chip provided with a large number of conductive surface pads made from aluminum or copper. A high temperature solder and a eutectic solder serve to join each pad on the chip to a corresponding pad on the ceramic or glass-epoxy substrate. The interconnect is then sealed in an under fill resin such as a controlled expansion epoxy encapsulant. Stresses, such as thermal stress, are absorbed by the two different solders used in the connections. Repairs can be readily made prior to the encapsulation in the under fill resin.
Ideally, it is important to ‘escape’ 100% of the signals out of a semiconductor chip through the underlying carrier substrate. This typically is achieved in a C4 assembly by making the substrate larger than the chip, and “fanning” the transmission lines, thereby distributing the signal elements over a larger surface area. Also, by employing multiple circuit layers in the substrate, the signals are passed through conductive vias into the multiple layers within the substrate. In C4 technology, the electrical connections are made by soldering each output from the chip to the selected signal layer within the substrate. If the signal output (escape) from the chip is less than 100%, then it becomes necessary to make the planar surface of the chip bigger, or to decrease the number of functional elements, e.g., microprocessor logic or memory, within the chip. Without the ability to use some of these elements, the overall functionality of the system suffers.
C4 area array interconnects provide numerous advantages for the semiconductor chip. Among these is the progression to higher performance, denser integration and reduced chip area along with enhanced reliability. At the macro level, C4 technology reduces product size and weight. Compared to other interconnect technology, the rework of components is facilitated.
The underlying carrier substrate is built up on a core that typically comprises one or two voltage/ground planes that are separated from one another and are bonded into a unitary assembly by a glass-reinforced dielectric. From one to four layers are laminated on each side of this core to provide signal planes, stability and wiring to and from the core. This structure supports chips as well as other active and passive components mounted on the surface of the structure. Microvias pass signals through the carrier substrate to the printed wiring board to which the carrier is coupled by a ball grid array or similar system.